![[ICO]](/icons/blank.gif){kind=icon}
![[PARENTDIR]](/icons/back.gif){kind=icon}
![[DIR]](/icons/folder.gif){kind=icon}
| Name | Last modified | Size | Description |
|---|---|---|---|---|
| Parent Directory | - | ||
| Intel/ | 2023-12-03 09:27 | - | |
| triggers/ | 2023-10-09 07:53 | - | |
| calling-conventions/ | 2022-11-21 06:15 | - | |
| transistors/ | 2022-09-12 17:36 | - | |
| mechanical-switches/ | 2022-09-12 17:36 | - | |
| CPU/ | 2022-09-12 17:36 | - | |
| Harvard-architecture/ | 2022-09-12 17:33 | - | |
| machines/ | 2022-02-25 13:40 | - | |
| circuits/ | 2021-09-13 14:50 | - | |
| logic-gates/ | 2021-09-12 21:26 | - | |
| neural-network/ | 2021-01-03 19:19 | - | |
| neurons/ | 2021-01-03 18:42 | - | |
| UMA/ | 2021-01-03 15:34 | - | |
| NORMA/ | 2021-01-03 15:34 | - | |
| NUMA/ | 2021-01-03 15:34 | - | |
| FPGA/ | 2021-01-03 12:29 | - | |
| von-Neumann-architecture-bottleneck/ | 2021-01-03 10:13 | - | |
| Harvard-CPU-Logisim/ | 2020-12-21 05:49 | - | |
| caches/ | 2020-11-29 18:50 | - | |
| pages/ | 2020-11-29 18:09 | - | |
| segments/ | 2020-11-29 18:09 | - | |
| memory-alignment/ | 2020-11-16 08:00 | - | |
| multipliers/ | 2020-10-15 17:54 | - | |
| registers/ | 2020-10-15 17:54 | - | |
| adders/ | 2020-10-15 17:54 | - | |
| counters/ | 2020-10-15 17:54 | - | |
| oscillators/ | 2020-10-15 17:54 | - | |
| decoders/ | 2020-10-15 17:54 | - | |
| integrator/ | 2020-10-11 17:24 | - | |
| 3-state-bus/ | 2020-10-11 15:59 | - | |
| encoders/ | 2020-10-11 15:46 | - | |
| multiplexers/ | 2020-10-11 15:25 | - | |
| ROM/ | 2020-10-04 09:39 | - | |
| RAM/ | 2020-10-04 09:39 | - | |
| automata/ | 2020-09-13 16:36 | - | |
| sequential/ | 2020-09-13 16:36 | - | |