Index of /~saulius/paskaitos/VU/kompiuterių-architektūra/skaidrės/drawings/logic-gates

[ICO]NameLast modifiedSizeDescription
[PARENTDIR]Parent Directory  -  
[IMG]constant-1-Boolean-function.png2020-09-02 07:27 535  
[IMG]constant-0-Boolean-function.png2020-09-02 07:27 550  
[IMG]identity-Boolean-function.png2020-09-02 07:27 643  
[IMG]NOT-Boolean-function.png2020-09-02 07:27 690  
[IMG]NOT-from-NAND-input-0.png2020-09-02 07:27 777  
[IMG]AND-gate-A0-B0.png2020-09-02 07:27 788  
[IMG]NAND-gate-A0-B0.png2020-09-02 07:27 817  
[IMG]NAND-gate-A1-B1.png2020-09-02 07:27 817  
[IMG]OR-gate-A1-B1.png2020-09-02 07:27 846  
[IMG]NOT-AND-NOT-A1-B1.png2020-09-02 07:27 847  
[IMG]NOT-AND-NOT-A0-B0.png2020-09-02 07:27 849  
[IMG]NOT-NAND-A0-B0.png2020-09-02 07:27 849  
[IMG]OR-gate-A0-B0.png2020-09-02 07:27 855  
[IMG]NAND-gate-A0-B1.png2020-09-02 07:27 863  
[IMG]NAND-gate-A1-B0.png2020-09-02 07:27 868  
[IMG]XOR-A0-B0.png2020-09-02 07:27 869  
[IMG]AND-NOT-A0-B0.png2020-09-02 07:27 887  
[IMG]NOT-NOR-A0-B0.png2020-09-02 07:27 901  
[IMG]NOT-AND-NOT-A0-B1.png2020-09-02 07:27 907  
[IMG]NOT-AND-NOT-A1-B0.png2020-09-02 07:27 908  
[IMG]OR-gate-A0-B1.png2020-09-02 07:27 909  
[IMG]OR-gate-A1-B0.png2020-09-02 07:27 910  
[IMG]AND-gate-A1-B1.png2020-09-02 07:27 1.0K 
[IMG]AND-from-NAND-A0-B0.png2020-09-02 07:27 1.0K 
[IMG]AND-gate-A0-B1.png2020-09-02 07:27 1.0K 
[IMG]NAND-alt-cropped-A0-B0.png2020-09-13 13:30 1.0K 
[IMG]OR-from-NAND-A1-B1.png2020-09-02 07:27 1.2K 
[IMG]OR-from-NAND-A0-B0.png2020-09-02 07:27 1.2K 
[IMG]3-input-odd-parity-all-1.png2020-11-15 16:40 1.2K 
[IMG]4-input-AND-from-2input-gates-all-1.png2020-09-02 07:27 1.2K 
[IMG]OR-from-NAND-A1-B0.png2020-09-02 07:27 1.3K 
[IMG]OR-from-NAND-A0-B1.png2020-09-02 07:27 1.3K 
[IMG]4-input-AND-from-2input-gates-one-0.png2020-09-02 07:27 1.3K 
[IMG]3-input-NOR-gate-all-0.png2020-09-02 07:27 1.5K 
[IMG]NOR-gate-A1-B1.png2021-09-12 20:29 1.6K 
[IMG]XOR-synthesis-A0-B0.png2020-09-02 07:27 1.6K 
[IMG]XOR-synthesis-A1-B1.png2020-09-02 07:27 1.6K 
[IMG]NOR-gate-A0-B0.png2021-09-12 20:29 1.6K 
[IMG]NOR-gate-A0-B1.png2021-09-12 20:29 1.6K 
[IMG]XOR-synthesis-A0-B1.png2020-09-02 07:27 1.6K 
[IMG]3-input-XOR-as-M2-all-1.png2020-11-15 16:40 1.6K 
[IMG]XOR-synthesis-A1-B0.png2020-09-02 07:27 1.6K 
[IMG]NOR-NOT-A0-B0.png2021-09-12 21:26 1.7K 
[IMG]3-input-NOR-RTL-gate-all-0.png2020-09-02 07:27 1.8K 
[ ]NOT-from-NAND.circ2020-09-02 07:27 2.3K 
[ ]NAND-alt.circ2020-09-13 13:30 2.3K 
[ ]OR.circ2020-09-02 07:27 2.5K 
[ ]AND.circ2020-09-02 07:27 2.5K 
[ ]NOR.circ2020-09-02 07:27 2.5K 
[ ]XOR.circ2020-09-02 07:27 2.5K 
[ ]NAND.circ2020-09-02 07:27 2.5K 
[ ]NOT-NOR.circ2020-09-02 07:27 2.5K 
[ ]NOT-AND-NOT.circ2020-09-02 07:27 2.5K 
[ ]NOT-NAND.circ2020-09-02 07:27 2.5K 
[ ]AND-NOT.circ2020-09-02 07:27 2.6K 
[ ]NOR-NOT.circ2021-09-12 21:26 2.6K 
[IMG]3-input-XOR-all-1.png2020-11-15 16:14 2.6K 
[ ]3-input-XOR.circ2020-11-15 16:14 2.6K 
[ ]odd-parity.circ2020-11-15 16:40 2.6K 
[ ]AND-from-NAND.circ2020-09-02 07:27 2.7K 
[ ]constant-1-Boolean-function.xcf2020-09-02 07:27 2.9K 
[ ]OR-from-NAND.circ2020-09-02 07:27 3.0K 
[ ]constant-0-Boolean-function.xcf2020-09-02 07:27 3.0K 
[ ]XOR-synthesis.circ2020-09-02 07:27 3.2K 
[ ]4-input-AND-from-2-input-gates.circ2020-09-02 07:27 3.3K 
[ ]identity-Boolean-function.xcf2020-09-02 07:27 3.6K 
[ ]NOT-Boolean-function.xcf2020-09-02 07:27 3.7K 
[ ]3-input-NOR-gate.circ2020-10-04 09:39 4.5K 
[ ]NOT-from-NAND-input-1.xcf2020-09-02 07:27 5.5K 
[ ]NAND-alt-cropped-A0-B0.xcf2020-09-13 13:30 5.6K 
[ ]NOT-from-NAND-input-0.xcf2020-09-02 07:27 5.8K 
[ ]3-input-NOR-RTL-gate.circ2020-10-04 09:39 5.8K 
[ ]NOR-gate-A1-B1.xcf2021-09-12 20:29 6.3K 
[ ]NOR-gate-A0-B0.xcf2021-09-12 20:29 6.4K 
[ ]NOR-gate-A0-B1.xcf2021-09-12 20:29 6.4K 
[ ]NOR-gate-A1-B0.xcf2021-09-12 20:29 6.4K 
[ ]OR-gate-A1-B1.xcf2020-09-02 07:27 6.5K 
[ ]OR-gate-A0-B1.xcf2020-09-02 07:27 6.6K 
[ ]OR-gate-A1-B0.xcf2020-09-02 07:27 6.6K 
[ ]AND-gate-A1-B1.xcf2020-09-02 07:27 6.6K 
[ ]NAND-gate-A0-B1.xcf2020-09-02 07:27 6.7K 
[ ]NAND-gate-A1-B0.xcf2020-09-02 07:27 6.7K 
[ ]NAND-gate-A1-B1.xcf2020-09-02 07:27 6.7K 
[ ]AND-gate-A0-B0.xcf2020-09-02 07:27 6.7K 
[ ]XOR-as-M2.circ2020-11-15 16:40 6.7K 
[ ]NAND-gate-A0-B0.xcf2020-09-02 07:27 6.8K 
[ ]OR-gate-A0-B0.xcf2020-09-02 07:27 6.8K 
[ ]NOT-AND-NOT-A1-B1.xcf2020-09-02 07:27 6.8K 
[ ]AND-gate-A0-B1.xcf2020-09-02 07:27 6.8K 
[ ]NOT-AND-NOT-A0-B1.xcf2020-09-02 07:27 6.9K 
[ ]NOT-AND-NOT-A1-B0.xcf2020-09-02 07:27 6.9K 
[ ]NOT-AND-NOT-A0-B0.xcf2020-09-02 07:27 7.1K 
[ ]NOT-NAND-A0-B0.xcf2020-09-02 07:27 7.1K 
[ ]NOT-NOR-A0-B0.xcf2020-09-02 07:27 7.2K 
[ ]XOR-A0-B0.xcf2020-09-02 07:27 7.4K 
[ ]NOR-NOT-A0-B0.xcf2021-09-12 21:26 7.5K 
[ ]AND-NOT-A0-B0.xcf2020-09-02 07:27 7.8K 
[ ]AND-from-NAND-A0-B0.xcf2020-09-02 07:27 9.7K 
[ ]NAND-alt-A0-B0.xcf2020-09-13 13:30 12K 
[ ]OR-from-NAND-A1-B1.xcf2020-09-02 07:27 12K 
[ ]all-one-input-Boolean-functions.xcf2020-09-02 07:27 12K 
[ ]OR-from-NAND-A0-B1.xcf2020-09-02 07:27 12K 
[ ]OR-from-NAND-A1-B0.xcf2020-09-02 07:27 12K 
[ ]OR-from-NAND-A0-B0.xcf2020-09-02 07:27 12K 
[ ]3-input-odd-parity-all-1.xcf2020-11-15 16:40 14K 
[ ]4-input-AND-from-2input-gates-all-1.xcf2020-09-02 07:27 15K 
[ ]4-input-AND-from-2input-gates-one-0.xcf2020-09-02 07:27 15K 
[ ]3-input-XOR-all-1.xcf2020-11-15 16:14 16K 
[ ]XOR-synthesis-A0-B1.xcf2020-09-02 07:27 17K 
[ ]XOR-synthesis-A1-B0.xcf2020-09-02 07:27 17K 
[ ]XOR-synthesis-A1-B1.xcf2020-09-02 07:27 17K 
[ ]XOR-synthesis-A0-B0.xcf2020-09-02 07:27 17K 
[ ]3-input-XOR-as-M2-all-1.xcf2020-11-15 16:40 17K 
[ ]3-input-NOR-gate-all-0.xcf2020-09-02 07:27 28K 
[ ]3-input-NOR-RTL-gate-all-0.xcf2020-09-02 07:27 35K 
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