% Encoding: UTF-8

@Manuscript{Waterman2011,
  author    = {Waterman, Andrew and Lee, Yunsup and Patterson, David and Asanović, Krste},
  title     = {The {RISC-V} instruction set manual. {V}olume {I}: base user-level {ISA}. {V}ersion 1.0},
  year      = {2011},
  keywords  = {CS, computer architecture, RISC},
  url       = {https://inst.eecs.berkeley.edu/~cs250/fa11/handouts/riscv-spec.pdf},
  file      = {:by-author/W/Waterman/2011_Waterman.pdf:PDF},
  owner     = {saulius},
  timestamp = {2019.02.17},
}

@TechReport{Celio2015,
  author      = {Christopher Celio and David A. Patterson and Krste Asanović},
  institution = {The Engineering and Computer Sciences, University of {C}alifornia at {B}erkeley},
  title       = {{B}erkeley out-of-order machine ({BOOM}): an industry-competitive, synthesizable, parameterized {RISC-V} processor},
  year        = {2015},
  number      = {Technical Report No. UCB/EECS-2015-167},
  file        = {:by-author/C/Celio/2015_Celio_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, out-of-order execution, computer architecture},
  owner       = {saulius},
  pages       = {1--5},
  timestamp   = {2020.07.26},
  url         = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-167.pdf},
}

@Article{Clark2017,
  author    = {Clark, Michael and Hoult, Bruce},
  title     = {{rv8}: a high performance {RISC-V} to x86 binary translator},
  year      = {2017},
  pages     = {1--7},
  doi       = {10.13140/RG.2.2.30957.69601},
  file      = {:by-author/C/Clark/2017_Clark_1.pdf:PDF},
  owner     = {saulius},
  publisher = {ResearchGate},
  timestamp = {2020.08.05},
}

@TechReport{RISCVTeam2019,
  author      = {{RISCV Team}},
  institution = {RISC-V Project},
  title       = {{RISC-V} "{V}" vector extension, version 0.8},
  year        = {2019},
  address     = {https://github.com/riscv},
  file        = {:by-author/R/RISCVTeam/2019_RISCVTeam_1.pdf:PDF},
  keywords    = {CS, RISC-V, computer architecture, vector architecture},
  owner       = {saulius},
  pages       = {1--103},
  timestamp   = {2020.08.05},
  url         = {https://github.com/riscv/riscv-v-spec/releases/download/0.8/riscv-v-spec-0.8.pdf},
}

@TechReport{Waterman2014,
  author      = {Andrew Waterman and Yunsup Lee and David A. Patterson and Krste Asanovic},
  institution = {Electrical Engineering and Computer Sciences, University of California at Berkeley},
  title       = {The {RISC-V} instruction set manual, volume {I}: user-level {ISA}, version 2.0},
  year        = {2014},
  number      = {UCB/EECS-2014-54},
  file        = {:by-author/W/Waterman/2014_Waterman_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--102},
  timestamp   = {2020.12.06},
  url         = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-54.pdf},
}

@TechReport{Waterman2015,
  author      = {Andrew Waterman and Yunsup Lee and David A. Patterson and Krste Asanović},
  institution = {Electrical Engineering and Computer Sciences, University of California at Berkeley},
  title       = {The {RISC-V} compressed instruction set manual, version 1.9},
  year        = {2015},
  month       = nov,
  number      = {UCB/EECS-2015-209},
  type        = {techreport},
  file        = {:by-author/W/Waterman/2015_Waterman_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--23},
  timestamp   = {2020.12.06},
  url         = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-209.pdf},
}

@TechReport{Asanovic2014,
  author      = {Krste Asanović and David A. Patterson},
  institution = {Electrical Engineering and Computer Sciences, University of California at Berkeley},
  title       = {Instruction sets should be free: the case for {RISC-V}},
  year        = {2014},
  file        = {:by-author/A/Asanović/2014_Asanović_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--7},
  timestamp   = {2020.12.06},
  url         = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2014/EECS-2014-146.pdf},
}

@TechReport{Waterman2015a,
  author      = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The {RISC-V} compressed instruction set manual, version 1.7},
  year        = {2015},
  month       = {May},
  number      = {UCB/EECS-2015-157},
  abstract    = {This is a draft specification version 1.7 of the RISC-V Compressed ISA extension. This draft specification will change before being accepted as standard, so implementations made to this draft specification will likely not conform to the future standard.},
  file        = {:by-author/W/Waterman/2015_Waterman_1a.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-157.html},
}

@TechReport{Waterman2015b,
  author      = {Waterman, Andrew and Lee, Yunsup and Avizienis, Rimas and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The {RISC-V} instruction set manual volume {II}: privileged architecture version 1.7},
  year        = {2015},
  month       = {May},
  number      = {UCB/EECS-2015-49},
  abstract    = {This is a draft specification version 1.7 of the RISC-V Privileged Architecture.  This draft specification will change before being accepted as standard, so implementations made to this draft specification will likely not
conform to the future standard.},
  file        = {:by-author/W/Waterman/2015_Waterman_1b.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2015/EECS-2015-49.html},
}

@TechReport{Waterman2016,
  author      = {Waterman, Andrew and Lee, Yunsup and Avizienis, Rimas and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The {RISC-V} instruction set manual volume {II}: privileged architecture version 1.9.1},
  year        = {2016},
  month       = {Nov},
  number      = {UCB/EECS-2016-161},
  file        = {:by-author/W/Waterman/2016_Waterman_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--89},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.html},
}

@TechReport{Celio2016,
  author      = {Celio, Christopher and Dabbelt, Daniel and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The renewed case for the reduced instruction set computer: avoiding {ISA} bloat with macro-op fusion for {RISC-V}},
  year        = {2016},
  month       = {Jul},
  number      = {UCB/EECS-2016-130},
  abstract    = {This report makes the case that a well-designed Reduced Instruction Set Computer (RISC) can match, and even exceed, the performance and code density of existing commercial Complex Instruction Set Computers (CISC) while maintaining the simplicity and cost-effectiveness that underpins the original RISC goals.

We begin by comparing the dynamic instruction counts and dynamic instruction bytes fetched for the popular proprietary ARMv7, ARMv8, IA-32, and x86-64 Instruction Set Architectures (ISAs) against the free and open RISC-V RV64G and RV64GC ISAs when running the SPEC CINT2006 benchmark suite. RISC-V was designed as a very small ISA to support a wide range of implementations, and has a less mature compiler toolchain. However, we observe that on SPEC CINT2006 RV64G executes on average 16% more instructions than x86-64, 3% more instructions than IA-32, 9% more instructions than ARMv8, but 4% fewer instructions than ARMv7.

CISC x86 implementations break up complex instructions into smaller internal RISC-like micro-ops, and the RV64G instruction count is within 2% of the x86-64 retired micro-op count. RV64GC, the compressed variant of RV64G, is the densest ISA studied, fetching 8% fewer dynamic instruction bytes than x86-64. We observed that much of the increased RISC-V instruction count is due to a small set of common multi-instruction idioms.

Exploiting this fact, the RV64G and RV64GC effective instruction count can be reduced by 5.4% on average by leveraging macro-op fusion. Combining the compressed RISC-V ISA extension with macro-op fusion provides both the densest ISA and the fewest dynamic operations retired per program, reducing the motivation to add more instructions to the ISA. This approach retains a single simple ISA suitable for both low-end and high-end implementations, where high-end implementations can boost performance through microarchitectural techniques.},
  file        = {:by-author/C/Celio/2016_Celio_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--18},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-130.html},
}

@TechReport{Waterman2016a,
  author      = {Waterman, Andrew and Lee, Yunsup and Avizienis, Rimas and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The {RISC-V} instruction set manual volume {II}: privileged architecture version 1.9.1},
  year        = {2016},
  month       = {Nov},
  number      = {UCB/EECS-2016-161},
  file        = {:by-author/W/Waterman/2016_Waterman_1a.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--89},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.html},
}

@TechReport{Waterman2016b,
  author      = {Waterman, Andrew and Lee, Yunsup and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {The {RISC-V} instruction set manual, volume {I}: user-level {ISA}, version 2.1},
  year        = {2016},
  month       = {May},
  number      = {UCB/EECS-2016-118},
  file        = {:by-author/W/Waterman/2016_Waterman_1b.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--133},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-118.html},
}

@PhdThesis{Waterman2016c,
  author      = {Waterman, Andrew},
  school      = {EECS Department, University of California, Berkeley},
  title       = {Design of the {RISC-V} instruction set architecture},
  year        = {2016},
  month       = {Jan},
  abstract    = {The hardware-software interface, embodied in the instruction set architecture (ISA), is arguably the most important interface in a computer system. Yet, in contrast to nearly all other interfaces in a modern computer system, all commercially popular ISAs are proprietary. A free and open ISA standard has the potential to increase innovation in microprocessor design, reduce computer system cost, and, as Moore’s law wanes, ease the transition to more specialized computational devices.

In this dissertation, I present the RISC-V instruction set architecture. RISC-V is a free and open ISA that, with three decades of hindsight, builds and improves upon the original Reduced Instruction Set Computer (RISC) architectures. It is structured as a small base ISA with a variety of optional extensions. The base ISA is very simple, making RISC-V suitable for research and education, but complete enough to be a suitable ISA for inexpensive, low- power embedded devices. The optional extensions form a more powerful ISA for general- purpose and high-performance computing. I also present and evaluate a new RISC-V ISA extension for reduced code size, which makes RISC-V more compact than all popular 64-bit ISAs.},
  file        = {:by-author/W/Waterman/2016_Waterman_1c.pdf:PDF},
  institution = {Electrical Engineering and Computer Sciences, University of California at Berkeley},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  number      = {UCB/EECS-2016-1},
  owner       = {saulius},
  pages       = {1--117},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-1.html},
}

@TechReport{Chen2016,
  author      = {Chen, Tony and Patterson, David A.},
  institution = {EECS Department, University of California, Berkeley},
  title       = {{RISC-V} geneology},
  year        = {2016},
  month       = jan,
  number      = {UCB/EECS-2016-6},
  type        = {techreport},
  file        = {:by-author/C/Chen/2016_Chen_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--8},
  timestamp   = {2020.12.06},
  url         = {https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-6.pdf},
}

@TechReport{Celio2017,
  author      = {Celio, Christopher and Chiu, Pi-Feng and Nikolic, Borivoje and Patterson, David A. and Asanović, Krste},
  institution = {EECS Department, University of California, Berkeley},
  title       = {{BOOM} v2: an open-source out-of-order {RISC-V} core},
  year        = {2017},
  month       = {Sep},
  number      = {UCB/EECS-2017-157},
  abstract    = {This paper presents BOOM version 2, an updated version of the Berkeley Out-of-Order Machine. The design exploration was performed through synthesis, place and route using the foundry-provided standard-cell library and the memory compiler in the TSMC 28 nm HPM process (high performance mobile).

BOOM is an open-source processor that implements the RV64G RISC-V Instruction Set Architecture (ISA). Like most contemporary high-performance cores, BOOM is superscalar (able to execute multiple instructions per cycle) and out-of-order (able to execute instructions as their dependencies are resolved and not restricted to their program order).  BOOM is implemented as a parameterizable generator written using the Chisel hardware construction language that can used to generate synthesizable implementations targeting both FPGAs and ASICs.

Managing the complexity of the register file was the largest obstacle to improving BOOM's clock frequency. We spent considerable effort on placing-and-routing a semi-custom 9-port register file to explore the potential improvements over a fully synthesized design, in conjunction with microarchitectural techniques to reduce the size and port count of the register file. BOOMv2 has a 37 fanout-of-four (FO4) inverter delay after synthesis and 50 FO4 after place-and-route, a 24\% reduction from BOOMv1's 65 FO4 after place-and-route. Unfortunately, instruction per cycle (IPC) performance drops up to 20\%, mostly due to the extra latency between load instructions and dependent instructions. However, the new BOOMv2 physical design paves the way for IPC recovery later.},
  file        = {:by-author/C/Celio/2017_Celio_1.pdf:PDF},
  keywords    = {CS, RISC, RISC-V, computer architecture, CPU design},
  owner       = {saulius},
  pages       = {1--8},
  timestamp   = {2020.12.06},
  url         = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-157.html},
}

@MastersThesis{Li2019,
  author    = {Li, Peijie},
  school    = {EECS Department, University of California, Berkeley},
  title     = {Reduce Static Code Size and Improve RISC-V Compression},
  year      = {2019},
  month     = {Jun},
  file      = {:by-author/L/Li/2019_Li_1.pdf:PDF},
  keywords  = {CS, RISC, RISC-V, computer architecture, CPU design},
  number    = {UCB/EECS-2019-107},
  owner     = {saulius},
  pages     = {1--39},
  timestamp = {2020.12.06},
  url       = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-107.html},
}

@MastersThesis{Amid2019,
  author    = {Amid, Alon},
  school    = {EECS Department, University of California, Berkeley},
  title     = {Nested-parallelism {PageRank} on {RISC-V} vector multi-processors},
  year      = {2019},
  month     = {Apr},
  abstract  = {Graph processing kernels and sparse-representation linear algebra workloads such as PageRank are increasingly used in machine learning and graph analytics contexts. While data-parallel processing and chip-multiprocessors have both been used in recent years as complementary mitigations to the slowing rate of single-thread performance improvements, they have been used together most efficiently on dense data-structure representations as opposed to sparse representations. This work presents nested-parallelism implementations of PageRank for RISC-V multi-processor Rocket chip SoCs with vector architecture accelerators. These software implementations are used for hardware and software design-space exploration using FPGA-accelerated simulation with multiple silicon-proven multi-processor SoC configurations. The design space includes a variety of scalar cores, vector accelerator cores, and cache parameters, as well as multiple software implementations with tunable parallelism parameters. This report shows the benefits of the loop-raking vectorizing technique
compared to an alternative vectoring technique, and presents up to a 14x run-time speedup relative to a parallel-scalar implementation running on the same SoC configuration. A 25x speedup is demonstrated in a dual-tile SoC with dual-lanes-per-tile vector accelerators, compared to a minimal scalar implementation, demonstrating the scalability of the proposed nested-parallelism techniques.},
  editor    = {Nikolic, Borivoje and Asanović, Krste},
  file      = {:by-author/A/Amid/2019_Amid_1.pdf:PDF},
  keywords  = {CS, RISC, RISC-V, computer architecture, CPU design},
  number    = {UCB/EECS-2019-6},
  owner     = {saulius},
  pages     = {1--64},
  timestamp = {2020.12.06},
  url       = {http://www2.eecs.berkeley.edu/Pubs/TechRpts/2019/EECS-2019-6.html},
}

@Manuscript{Underwood2019,
  author    = {Alex Underwood and Tuan Nguyen and James E. Stine},
  title     = {{IEEE} floating-point extension for containing error in the {RISC-V} architecture},
  year      = {2019},
  keywords  = {CS, RISC, RISC-V, computer architecture, CPU design, floating point},
  url       = {https://carrv.github.io/2019/papers/carrv2019_paper_11.pdf},
  comment   = {DOI is broken...},
  file      = {:by-author/U/Underwood/2019_Underwood_1.pdf:PDF},
  owner     = {saulius},
  pages     = {1--6},
  timestamp = {2020.12.06},
}

@Manuscript{Amid2019a,
  author    = {Amid, Alon and Asanovic, Krste and Baum, Allen and Bradbury, Alex and Brewer, Tony and Celio, Chris and AliakseiChapyzhenka and Chiricescu, Silviu and Dockser, Ken and Dreyer, Bob and Espasa, Roger and Halle, Sean and Hauser, John and Horner, David and Hoult, Bruce and Huffman, Bill and Korikov, Constantine and Korpan, Ben and Kruppe, Robin and Lee, Yunsup and Lemieux, Guy and Moc, Filip and RichNewell and Ou, Albert and Patterson, David and Schmidt, Colin and Solomatnikov, Alex and Wallach, Steve and Waterman, Andrew and Wilson, Jim},
  title     = {{RISC-V} "{V}" vector extension},
  year      = {2019},
  keywords  = {CS, RISC, RISC-V, computer architecture, CPU design, vector architectures},
  url       = {https://riscv.github.io/documents/riscv-v-spec/riscv-v-spec.pdf},
  file      = {:by-author/A/Amid/2019_Amid_1a.pdf:PDF},
  owner     = {saulius},
  timestamp = {2020.12.06},
}

@Manuscript{Porter2018,
  author    = {Porter, III, Harry H.},
  title     = {{RISC-V}: an overview of the instruction set architecture},
  year      = {2018},
  keywords  = {CS, RISC, RISC-V, computer architecture, CPU design},
  url       = {https://web.cecs.pdx.edu/~harry/riscv/RISCV-Summary.pdf},
  file      = {:by-author/P/Porter/2018_Porter_1.pdf:PDF},
  owner     = {saulius},
  pages     = {1--323},
  timestamp = {2020.12.06},
}