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%$Author: saulius $
%$Date: 2020-06-04 14:58:32 +0300 (Thu, 04 Jun 2020) $ 
%$Revision: 1524 $
%$URL: svn+ssh://saulius-grazulis.lt/home/saulius/svn-repositories/seminarai/2020-verifikacjos-seminarui/slides.tex $
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% "Use an OpenType clone of Bookman, for instance TeX Gyre Bonum":
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%\addbibresource{bibliography/citations.bib}
\addbibresource{bibliography/Intel.bib}
\addbibresource{bibliography/AMD.bib}
\addbibresource{bibliography/Jorgensen.bib}
\addbibresource{bibliography/Domas.bib}
\addbibresource{bibliography/Dolan.bib}
\newcommand{\mycite}{\parencite}


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%%BEGIN LANGUAGE en
\title{Intel x86 CPU architecture}
%%END LANGUAGE en


\author{Saulius Gražulis}

\date{Vilnius, 2020}

% Define colors as in
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\begin{document}

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%------------------------------------------------------------------------------

\begin{frame}
    \titlepage

\input{affiliation}
    
    \begin{center}
      \mbox{}
      \hfill\hfill\hfill
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    %% \tiny
    %% \RCSid{
    %%   $Id: slides.tex 1524 2020-06-04 11:58:32Z saulius $
    %% }
    \begin{flushright}
      \begin{minipage}[c]{0.67\textwidth}
        \tiny\raggedright
        %%BEGIN LANGUAGE en
        This set of slides may be copied and used as specified in the
        %%END LANGUAGE en
        \myhref{http://creativecommons.org/licenses/by-sa/4.0/}{Attribution-ShareAlike
          4.0 International}
license
      \end{minipage}
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          \includegraphics[width=1.5cm]{images/CC-BY-SA.eps}
        }
      \end{minipage}
    \end{flushright}

\end{frame}

%==============================================================================

\begin{frame}
\frametitle{What is a processor architecture?}

  \begin{center}
    %%BEGIN LANGUAGE en
    Architecture visible to programmer:
    %%END LANGUAGE en



    \begin{itemize}
    \item
      \color{gray}
      %%BEGIN LANGUAGE en
      The CPU registers visible to programmer
      %%END LANGUAGE en


    \item
      %%BEGIN LANGUAGE en
      Memory addressing
      %%END LANGUAGE en


    \item
      %%BEGIN LANGUAGE en
      Data formats
      %%END LANGUAGE en


    \item
      \color{black}
      %%BEGIN LANGUAGE en
      Processor instruction set
      %%END LANGUAGE en


    \item
      %%BEGIN LANGUAGE en
      Input-output
      %%END LANGUAGE en


    \item
      %%BEGIN LANGUAGE en
      Interrupt processing
      %%END LANGUAGE en


      
    \end{itemize}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Registers (x86)}

  \begin{center}
    Intel 8086 CPU
    
    \includegraphics[width=4cm]{drawings/Intel/8086-regs.eps}
  \end{center}
  
  \leftline{\scriptsize\mycite{INTEL1979}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Registers (x86\_64)}

  \begin{center}
    \includegraphics[page=36,width=11cm,trim=2cm 13.7cm 2cm 6cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}

  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Stack operation}

  \begin{center}
    \includegraphics[page=54,width=5cm,trim=3cm 16.6cm 10.8cm 8.2cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
    \includegraphics[page=54,width=5cm,trim=10.5cm 16.6cm 3cm 8cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction pointer}

  \begin{center}
    \includegraphics[page=55,width=7cm,trim=6.1cm 18cm 5cm 8.3cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Registers, Legacy and Compatibility modes}

  \begin{center}
    \includegraphics[page=59,width=7cm,trim=6.1cm 18cm 5cm 4cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Registers}

  \begin{center}
    \includegraphics[page=58,height=7cm,trim=4cm 9cm 4cm 5cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Segmented addressing}

  %%BEGIN LANGUAGE en
  Segment address is shifted by 4 bits and added to the offset:
  %%END LANGUAGE en

  \vspace{\baselineskip}
%%   \only<1>{
%%     \begin{center}
%%       \includegraphics[width=3cm]{drawings/Intel/8086-segments.eps}
%%     \end{center}
%%   }
%%  \only<2>{
    \begin{center}
      \includegraphics[width=7cm,page=28,trim=4cm 17cm 4cm 2cmcm,clip]{images/Intel-dokumentacija/Intel_8086_Family_Users_Manual_October_19-INTEL.pdf}
    \end{center}
%%  }

  \mycite{INTEL1979}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Flag register}

  \begin{center}
    \includegraphics[page=68,width=11cm,trim=2cm 10.5cm 2cm 11.4cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Flags}

  \begin{itemize}
  \item
    %%BEGIN LANGUAGE en
    \textbf{Carry Flag (CF)} -- 1 if the last integer addition or
    subtraction operation resulted in a carry (for addition) or a
    borrow (for subtraction) out of the most-significant bit position
    of the result. Increment and decrement instructions—unlike the
    addition and subtraction instructions—do not affect the carry
    flag.    
    %%END LANGUAGE en
  \item
\textbf{Overflow Flag (OF)}
  \item
\textbf{Auxiliary Overflow Flag (AF)}
  \item
    %%BEGIN LANGUAGE en
    \textbf{Parity Flag (PF)} -- 1 if there is an even number of 1 bits in the
    least-significant byte of the last result of certain operations.
    %%END LANGUAGE en
  \item
\textbf{Zero Flag (ZF)}
  \item
\textbf{Sign Flag (SF)}
  \item
\textbf{Directions Flag (DF)}
  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction types}

  \begin{itemize}
  \item
Data Movement
    
  \item
Conversion Instructions
    
  \item
Arithmetic Instructions

  \item
Logical Instructions

  \item
Control Instructions
Команды управления

  \end{itemize}

  \rightline{\scriptsize\mycite{Jorgensen2020}}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Zero extension of 32-bit operands}

  %%BEGIN LANGUAGE en
  As Figure 3-3 on page 27 and Figure 3-4 on page 28 show, when
  performing 32-bit operations with a GPR destination in 64-bit mode,
  the processor zero-extends the 32-bit result into the full 64-bit
  destination \mycite{AMD2017}, p.~29. 
  %%END LANGUAGE en

  

  \begin{center}
    \includegraphics[page=61,width=11cm,trim=4cm 19.9cm 2cm 4cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction syntax}

  \begin{center}
    \includegraphics[page=78,width=8cm,trim=6cm 7cm 6cm 18cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_1.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}}

  {\scriptsize\mywebref{https://en.wikipedia.org/wiki/X86\_instruction\_listings}}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Number of instructions – x86}

  \begin{itemize}
  \item
    %%BEGIN LANGUAGE en
    To the assembly language programmer, the 8086 and 8088 appear to
    have a repertoire of about 100 instructions. \mycite{INTEL1979}
    %% One MOV (move)
    %% instruction, for example, transfers a byte or a word from a
    %% register or a memory location or an immediate value to either a
    %% register or a memory location.
    %%END LANGUAGE en



  \item
    %%BEGIN LANGUAGE en
    The 8086 and 8088 CPUs, however, recognise 28 different MOV
    machine instructions (``move byte register to memory,'' ``move
    word immediate to register,'' etc.).
    %%END LANGUAGE en



    \begin{itemize}
    \item
      %%BEGIN LANGUAGE en
      ... \texttt{MOV} is actually Turing complete! \mycite{Dolan2013}
      %%END LANGUAGE en
    \end{itemize}
    
  \item
    %%BEGIN LANGUAGE en
    The x86\_64 architecture has roughly between 1000 and 3000
    instructions, depending on how you count...
    %%END LANGUAGE en
    \footnote{\tiny\mywebref{https://stefanheule.com/blog/how-many-x86-64-instructions-are-there-anyway}}

  \item
    %%BEGIN LANGUAGE en
    The x86\_64 architecture \textit{instruction space} (1-15 bytes)
    is $1.3\cdot{}10^{36}$ possible instructions. This can be reduced
    to a ``very manageable'' $\approx 10^{8}$ by a clever depth-first
    search \mycite{Domas2017}
    %%END LANGUAGE en
    
    
    
  \end{itemize}

  %% \leftline{\scriptsize Intel 8086 Family User's guide, p.~2-30}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Operand counts}

  \begin{itemize}
  \item
    %%BEGIN LANGUAGE en
    Zero-address machines:
    %%END LANGUAGE en
    \fbox{\texttt{OPCODE}}

  \item
    %%BEGIN LANGUAGE en
    One-address machines:
    %%END LANGUAGE en
    \fbox{\texttt{OPCODE}}\fbox{\texttt{OPERAND}}

  \item
    %%BEGIN LANGUAGE en
    Two-address machines:
    %%END LANGUAGE en
    \fbox{\texttt{OPCODE}}\fbox{\texttt{OP1}}\fbox{\texttt{OP2}}

  \item
    %%BEGIN LANGUAGE en
    Three-address machines:
    %%END LANGUAGE en
    \fbox{\texttt{OPCODE}}\fbox{\texttt{OP1}}\fbox{\texttt{OP2}}\fbox{\texttt{OP3}}

  \item
    %%BEGIN LANGUAGE en
    Four-address machines:
    %%END LANGUAGE en
    \fbox{\texttt{OPCODE}}\fbox{\texttt{OP1}}\fbox{\texttt{OP2}}\fbox{\texttt{OP3}}\fbox{\texttt{OP4}}

  \end{itemize}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction encoding – 8086}

  %%BEGIN LANGUAGE en
  Only one memory operand can be present!
  %%END LANGUAGE en
  
  \begin{center}
    \fbox{
    \includegraphics[page=161,width=11cm,trim=2cm 11.5cm 2cm 6cm,clip]{bibliography/PDF/Intel-8086-Family-users-manual.pdf}
    }
  \end{center}
  
  \leftline{\scriptsize Intel 8086 Family User's guide}
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Instruction encoding – 64 bit mode}

  \begin{center}
    \includegraphics[page=45,height=7cm,trim=3cm 13.3cm 12cm 4.5cm,clip]{images/AMD-dokumentacija/AMD64_Architecture_Programmers_Manual_Vol_3.pdf}
  \end{center}
  
  \leftline{\scriptsize\mycite{AMD2017}, Vol.~3}
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Register encoding – 8086}

  \begin{center}
    \includegraphics[page=162,width=6cm,trim=9cm 16cm 0.5cm 2cm,clip]{bibliography/PDF/Intel-8086-Family-users-manual.pdf}
  \end{center}
  
  \leftline{\scriptsize Intel 8086 Family User's guide, p.~162}
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Mode and register encoding – 8086}

  \begin{center}
    \includegraphics[page=162,width=11cm,trim=1.3cm 0.8cm 1.5cm 16.1cm,clip]{bibliography/PDF/Intel-8086-Family-users-manual.pdf}
  \end{center}
  
  \leftline{\scriptsize Intel 8086 Family User's guide, p.~162}
\end{frame}

%------------------------------------------------------------------------------

\lstset{
  keywordstyle=\color{KwdColor},
  commentstyle=\color{CommentColor}\ttfamily,
  identifierstyle=\color{IdentifierColor},
  stringstyle=\color{StringColor},
  basicstyle=\ttfamily\tiny
}

\begin{frame}
\frametitle{MOV instruction}

  \texttt{nasm}:
  \begin{center}
    \begin{minipage}{0.85\textwidth}
      \lstinputlisting[language=C,linerange={5-18,20-22},frame=trBL]{examples/assembler/x86-nasm/mov.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{LEA instruction}

  \texttt{nasm}:
  \begin{center}
    \begin{minipage}{0.85\textwidth}
      \lstinputlisting[language=C,linerange={5-15,20-22},frame=trBL]{examples/assembler/x86-nasm/lea.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{XCHG instruction}

  \begin{center}
    \begin{minipage}{0.7\textwidth}
      \lstinputlisting[language=C,linerange={5-11,15-16},frame=trBL]{examples/assembler/x86-nasm/xchg.lst}
    \end{minipage}
  \end{center}
  
  \begin{quote}
    \small
    If a memory operand is referenced, the processor's locking
    protocol is automatically implemented for the duration of the
    exchange operation, regardless of the presence or absence of the
    LOCK prefix or of the value of the IOPL. (See the LOCK prefix
    description in this chapter for more information on the locking
    protocol.) This instruction is useful for implementing semaphores
    or similar data structures for process synchronization.
  \end{quote}
  \rightline{\scriptsize\mywebref{https://c9x.me/x86/html/file\_module\_x86\_id\_328.html}}
  \rightline{\scriptsize 2020-03-23}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{ADD, ADC instructions}

  \texttt{nasm}:
  \begin{center}
    \begin{minipage}{0.7\textwidth}
      \lstinputlisting[language=C,linerange={5-15,20-22},frame=trBL]{examples/assembler/x86-nasm/add-adc.lst}
    \end{minipage}
  \end{center}

\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{INC, DEC instructions}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-10},frame=trBL]{examples/assembler/x86-nasm/inc-dec.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{REP STOS instruction}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-11,16-18},frame=trBL]{examples/assembler/x86-nasm/rep-stos.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{LOOP instruction}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-12},frame=trBL]{examples/assembler/x86-nasm/loop-imul.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{JMP,Jcc instructions}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-13},frame=trBL]{examples/assembler/x86-nasm/jmp-jcc.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{PUSH/POP instructions}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-13},frame=trBL]{examples/assembler/x86-nasm/push-pop.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{CALL and RET instructions}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      \lstinputlisting[language=C,linerange={5-6,11-12},frame=trBL]{examples/assembler/x86-nasm/call-ret.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}
\frametitle{Stack frame}

  \begin{center}
    \includegraphics[width=11cm]{drawings/calling-conventions/C-calling-convention.eps}
  \end{center}
  
\end{frame}

%% %------------------------------------------------------------------------------
%% 
%% \begin{frame}
%%   %%LANGUAGE en \frametitle{Calling conventions (16 bit)}
%%   %%LANGUAGE lt \frametitle{Kvietimo susitarimai}
%%   %%LANGUAGE ru \frametitle{Соглашения вызова}
%% 
%% \end{frame}
%% 
%% %------------------------------------------------------------------------------
%% 
%% \begin{frame}
%%   %%LANGUAGE en \frametitle{Calling conventions (64 bit)}
%%   %%LANGUAGE lt \frametitle{Kvietimo susitarimai (64 bitai)}
%%   %%LANGUAGE ru \frametitle{Соглашения вызова (64 разряда}
%% 
%% \end{frame}
%% 
%% %------------------------------------------------------------------------------

\begin{frame}
\frametitle{SYSCALL/INT and SYSRET/IRET instructions}

  \begin{center}
    \begin{minipage}{0.9\textwidth}
      16-bit (\texttt{nasm}): 
      \lstinputlisting[language=C,linerange={7-9},frame=trBL]{examples/assembler/x86-nasm/call-ret.lst}

      64-bit (\texttt{yasm}): 
      \lstinputlisting[language=C,linerange={8-11,26-28},frame=trBL]{examples/assembler/x86_64-yasm/try.lst}
    \end{minipage}
  \end{center}
  
\end{frame}

%------------------------------------------------------------------------------

\begin{frame}%%[allowframebreaks]
\frametitle{References}

  \renewcommand{\bibfont}{\scriptsize}
  \printbibliography

\end{frame}

%------------------------------------------------------------------------------                                                                                                          
\end{document}
% 2023-11-27 11:07:17 EET